AEPT Program Accomplishments:

Completed program month 41 of the 48 month effort:

  • TV-1 design, fabrication & laser trimming complete

  • TV-1 reliability assessment and characterization testing completed on 7 embedded passives (EP) capacitor/resistor materials. Baseline for industry comparison is set

  • TV-2 design and fabrication complete using 5 EP materials

  • Neural-net modeling completed on the TV2 ceramic resistor samples
    Baseline neural net model completed, populated with simulated data, and ready for TV-2 data input.

  • Design spec provided to the CAD tool developer

  • Laser trim equipment designed and built, successfully trimmed materials in TV-1, TV-2, and first OEM product emulator

  • MicroFab completed resistor printing with ink jet technology, EP resistor repair capability developed, critical cost and performance metrics established

  • Completed process flow, cost analysis, and modeling of AEPT embedded approaches. Web-based cost model and trade-off tool being fine tuned. Now running test vehicle (TV) and emulator data in model

  • AEPT program has four materials that meet our Phase-1 performance targets not including the trim down material

  • Expanded project scope & participants:

MicroFab - material jetting technology
ESI - embedded resistor test / trim technologies
Added product emulators to scope

  • OEM product emulator test vehicles are selected and progressing through development and fabrication

  • Cost model and trade-off tool completed and collaborated with the NEMI 2003 roadmap update

OEM Emulators:

Nortel emulator product -

  • Design is complete

Size reduction of 50% possible

Signal Integrity improvement of 20% - Elimination of component induction

Capacitive layers provide better immunity, less second order effects results in faster design cycle.

  • A second version design using ceramic resistor and C-Ply capacitor material is in progress

  • The PWB fabrication is complete

  • Laser trim technology was used

  • Component information has been delivered to Foresight for cost analysis

  • Electrical test is in process at Nortel

Delphi emulator product -

  • Reviewed 5 years of work by Delphi on emulators, design studies, paper cost studies preparing for choosing emulator candidate

  • Emulator product selected

  • Initial ceramic design guidelines established

  • Collected and suggested some basic resistor and capacitor minimum parameters

  • Design effort complete

  • Board fabrication in process at Coretec Denver

  • Laser trim technology will be used

Hewlett-Packard emulator product -

  • HP emulator product selected

  • Completed design translation from Mentor to Cadence

  • Will use DuPont ceramic technology

  • Design files have been completed and are in review by Merix/Coretec/DuPont

  • First pass design for manufacturability (DFM) is complete

Industry Interaction:

  • AEPT project participants have published and presented numerous technical papers at industry symposiums:

  • IPC, IMAPS, NEMI, APEX, CARTS, IEMT, Circuitree

  • These papers are available at www.aept.ncms.org

  • AEPT Project regularly interfaces with the IPC and NEMI membership

  • IPC Interface – IPC disseminates project information to the printed wiring board industry

  • AEPT leading the new IPC task group, Embedded Passive Devices Task, 3-12j - Several task group meetings have occurred in 2001 and 2002

  • Embedded Passive Board Design group met in July ’02 (chairman is Kim Fjeldsted - ESI)

  • Embedded Passive Test methods met in July ’02 (chairman is Jan Obrzut - NIST)

  • Completed draft of IPC Embedded Passives Board Performance Specification

  • These IPC activities are ongoing

UL Interface -

  • UL approval requirements identified and being addressed

  • AEPT raised the embedded passives test requirements question with UL in Feb/Apr 2001. Effort at UL test sites being coordinated

  • Technical contact is Thomas Farrell of UL Melville and completed projects contact is Lorinda Badalian in Santa Clara

  • AEPT interface on UL Standard 746E, 766, and flammability test 94-Vertical Burn

  • Resistors will be tested to some combination of bond strength, flame, blistering and delamination, and if applicable - silver migration. Testing determined by cure temperature of the resistor material

  • EP materials and board samples are undergoing UL testing

  • Planning fall 2002 Industry Advisory Group meeting with UL concerning embedded passives


     

© 2007
National Center for Manufacturing Sciences